Bài giảng "Thiết kế vi mạch số - TS. Trương Quang Vinh" gồm các nội dung sau: Thiết kế mạch tổ hợp, thiết kế mạch tuần tự, mô phỏng mạch và mô tả phần cứng ngôn ngữ. | Lecture 6: Circuit design – part 1 Combinational circuit design Sequential circuit design Circuit simulation . Hardware description language Combinational Circuit Design 1 1. Combinational circuit design Circuit designer must learn to think in terms of NAND and NOR to take advantage of static CMOS CMOS stages are inherently inverting, DeMorgan’s law helps with this conversion: Combinational Circuit Design CMOS VLSI Design 4th Ed. 2 1 1. Combinational circuit design Bubble Pushing – Start with network of AND / OR gates – Convert to NAND / NOR + inverters – Push bubbles around to simplify logic – Remember DeMorgan’s Law Combinational Circuit Design CMOS VLSI Design 4th Ed. 3 Example Example: Design a circuit to compute F = AB + CD using NANDs and NORs. Combinational Circuit Design CMOS VLSI Design 4th Ed. 4 2 Compound Gates Compound Gates – AOI21: AND-OR-INVERT-21 – AOI22: AND-OR-INVERT-22 Combinational Circuit Design CMOS VLSI Design 4th Ed. 5 Logical Effort of compound gates Combinational Circuit Design CMOS VLSI Design 4th Ed. 6 3 Example Example: – Calculate the minimum delay, in τ, to compute F = AB + CD using the following circuits: Using compound gate Using NAND gate – Each input can present a maximum of 20 λ of transistor width. The output must drive a load equivalent to 100 λ of transistor width. Combinational Circuit Design CMOS VLSI Design 4th Ed. 7 Example Solution: – The path electrical effort is H = 100/20 = 5 – The branching effort is B = 1 Using compound gate Using NAND gate No. of stages N = 2 Logical effort G = (4/3) × (4/3) = 16/9 Parasitic delay P = 2 + 2 = 4 Path efforts F = GBH = 80/9 Path delays D = NF1/N + P = N=2 G = (6/3) × 1 = 2 P = 12/3 + 1 = 5 F = GBH = 2×1×5 = 10 D = NF1/N + P = => Using compound gates does not always result in faster circuits; simple 2-input NAND gates can be quite fast. Combinational Circuit Design CMOS VLSI Design 4th Ed. 8 4 Input Order Our
