rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the line trise | Digital Integrated Circuits A Design Perspective The Wire Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic July 30, 2002 The Wire schematics physical Interconnect Impact on Chip Wire Models All-inclusive model Capacitance-only Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel INTERCONNECT Capacitance Capacitance of Wire Interconnect Capacitance: The Parallel Plate Model Permittivity Fringing Capacitance Fringing versus Parallel Plate Interwire Capacitance Impact of Interwire Capacitance Wiring Capacitances ( mm CMOS) INTERCONNECT Resistance Wire Resistance Interconnect Resistance Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length . | Digital Integrated Circuits A Design Perspective The Wire Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic July 30, 2002 The Wire schematics physical Interconnect Impact on Chip Wire Models All-inclusive model Capacitance-only Impact of Interconnect Parasitics Interconnect parasitics reduce reliability affect performance and power consumption Classes of parasitics Capacitive Resistive Inductive Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel INTERCONNECT Capacitance Capacitance of Wire Interconnect Capacitance: The Parallel Plate Model Permittivity Fringing Capacitance Fringing versus Parallel Plate Interwire Capacitance Impact of Interwire Capacitance Wiring Capacitances ( mm CMOS) INTERCONNECT Resistance Wire Resistance Interconnect Resistance Dealing with Resistance Selective Technology Scaling Use Better Interconnect Materials reduce average wire-length . copper, silicides More Interconnect Layers reduce average wire-length Polycide Gate MOSFET n + n + SiO 2 PolySilicon Silicide p Silicides: WSi 2, TiSi 2 , PtSi 2 and TaSi Conductivity: 8-10 times better than Poly Sheet Resistance Modern Interconnect Example: Intel micron Process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric INTERCONNECT Inductance Interconnect Modeling The Lumped Model The Lumped RC-Model The Elmore Delay The Ellmore Delay RC Chain Wire Model Assume: Wire modeled by N equal-length segments For large values of N: The Distributed RC-line The diffusion equation Step-response of RC wire as a function of time and space RC-Models Driving an RC-line Design Rules of Thumb rc delays should only be considered when tpRC >> tpgate of the driving gate Lcrit >> tpgate/ rc delays should only be considered when the rise (fall) time at the line input is smaller than RC, the rise (fall) time of the .