Chapter 16 covers the effect of a non-ideal clock signal and discusses the synchronization of an asynchronous signal and the interface between two independent clock domains. | Clock and Synchronization RTL Hardware Design by P. Chu Chapter 16 1 Outline 1. 2. 3. 4. Why synchronous? Clock distribution network and skew Multiple-clock system Meta-stability and synchronization failure 5. Synchronizer RTL Hardware Design by P. Chu Chapter 16 2 1. Why synchronous RTL Hardware Design by P. Chu Chapter 16 3 Timing of a combinational digital system • Steady state – Signal reaches a stable value – Modeled by Boolean algebra • Transient period – Signal may fluctuate – No simple model • Propagation delay: time to reach the steady state RTL Hardware Design by P. Chu Chapter 16 4 Timing Hazards • Hazards: the fluctuation occurring during the transient period – Static hazard: glitch when the signal should be stable – Dynamic hazard: a glitch in transition • Due to the multiple converging paths of an output port RTL Hardware Design by P. Chu Chapter .
