ARM Architecture Reference Manual- P21: The ARM instruction set architecture has evolved significantly since it was first developed, and will continue to be developed in the future. In order to be precise about which instructions exist in any particular ARM implementation, five major versions of the instruction set have been defined to date. | VFP Programmer s Model System registers A VFP implementation contains three or more special-purpose system registers The Floating-point System ID register FPSID is a read-only register whose value indicates which VFP implementation is being used. See FPSID on page C2-20 for details. The Floating-point Status and Control register FPSCR is a read write register which provides all user-level status and control of the floating-point system. See FPSCR on page C2-21 for details of the FPSCR. The Floating-point Exception register FPEXC is a read write register two bits of which provide system-level status and control. The remaining bits of this register can be used to communicate exception information between the hardware and software components of the implementation in an IMPLEMENTATION DEFINED manner. See FPEXC on page C2-24 for details of the FPEXC. Individual VFP implementations can define and use further system registers for the purpose of communicating between the hardware and software components of the implementation. All such registers are IMPLEMENTATION DEFINED. They may not be used outside the implementation itself except as described in implementation-specific documentation. ARM DDI 0100E Copyright 1996-2000 ARM Limited. All rights reserved. C2-19 VFP Programmer s Model FPSID The FPSID has the following format 31 24 23 22 21 20 19 16 15 8 7 4 3 0 implementor SW format SNG architecture part number variant revision Bits 31 24 Contain an implementor code. The following code is defined 0x41 A ARM Ltd All other values of the implementor code are reserved by ARM Ltd. Bit 23 Contains 0 if the implementation contains a hardware coprocessor or 1 if it is a pure software implementation. Bits 22 21 Indicate which FSTMX FLDMX format is used see Storing and reloading values of unknown precision on page C2-15 0b00 Indicates standard format 1. 0b01 Indicates standard format 2. 0b10 Is reserved. 0b11 Indicates a non-standard format. Bit 20 Contains 0 if the .
