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Báo cáo hóa học: " Research Article A High-End Real-Time Digital Film Processing Reconfigurable Platform"

Tham khảo luận văn - đề án 'báo cáo hóa học: " research article a high-end real-time digital film processing reconfigurable platform"', luận văn - báo cáo phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2007 Article ID 85318 15 pages doi 10.1155 2007 85318 Research Article A High-End Real-Time Digital Film Processing Reconfigurable Platform Sven Heithecker Amilcar do Carmo Lucas and Rolf Ernst Institute of Computer and Communication Network Engineering Technical University of Braunschweig 38106 Braunschweig Germany Received 15 May 2006 Revised 21 December 2006 Accepted 22 December 2006 Recommended by Juergen Teich Digital film processing is characterizedby a resolution of at least 2 K 2048 X 1536 pixels per frame at 30bit pixel and 24pictures s data rate of 2.2 Gbit s higher resolutions of 4 K 8.8 Gbit s and even 8 K 35.2 Gbit s are on their way. Real-time processing at this data rate is beyond the scope of today s standard and DSP processors and ASICs are not economically viable due to the small market volume. Therefore an FPGA-based approach was followed in the FlexFilm project. Different applications are supported on a single hardware platform by using different FPGA configurations. The multiboard multi-FPGA hardware software architecture is based on Xilinx Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path large SDRAM memories for multiple frame storage and a PCI-Express communication backbone network. The FPGA-embedded CPU is used for control and less computation intensive tasks. This paper will focus on three key aspects a the used design methodology which combines macro component configuration and macrolevel floorplaning with weak programmability using distributed microcoding b the global communication framework with communication scheduling and c the configurable multistream scheduling SDRAM controller with QoS support by access prioritization and traffic shaping. As an example a complex noise reduction algorithm including a 2.5-dimension discrete wavelet transformation DWT and a full 16 X 16 motion estimation ME at 24 fps requiring a total of 203