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Báo cáo hóa học: "Research Article Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intrapredictio"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intrapredictio | Hindawi Publishing Corporation EURASIP Journal on Advances in Signal Processing Volume 2008 Article ID 542735 19 pages doi 10.1155 2008 542735 Research Article Early Termination and Pipelining for Hardware Implementation of Fast H.264 Intraprediction Targeting Mobile HD Applications Jin-Su Jung Genhua Jin and Hyuk-Jae Lee School of Electrical Engineering and Computer Science Seoul National University Seoul 151-742 South Korea Correspondence should be addressed to Hyuk-Jae Lee hjlee_paper@capp.snu.ac.kr Received 2 March 2008 Revised 16 June 2008 Accepted 7 August 2008 Recommended by Liang-Gee Chen H.264 AVC adopts aggressive compression algorithms at the cost of increased computational complexity. To speed up the H.264 AVC intraframe coding this paper proposes two novel techniques early termination and pipelined execution. In P slices intra 4 X 4and16 X 16 predictions are early terminated with the threshold determined by the cost of motion estimation. In I slices intra 4 X 4 prediction is early terminated with the threshold derived from intra 16 X 16 prediction. The threshold function is chosen as a monotonically decreasing linear function with its optimal coefficients determined by experiments. For the pipelined execution of 4x4 intrapredictions the processing order of 4x4 blocks is changed to reduce the dependencies between consecutively processed blocks. In I slices computation for 4 X 4 intraprediction is reduced by 19 percent with the proposed early termination. In P slices computations for 4 X 4 and 16 X 16 intrapredictions are reduced by more than 81 and 91 percents respectively. The pipelined execution reduces the computation time by 41 percent. In spite of the speed-up by the proposed methods degradation in ratedistortion performance is negligible. The proposed pipelined execution is integrated with other H.264 AVC hardware accelerators and fabricated as an SoC using Dongbu 0.13 pm technology. Copyright 2008 Jin-Su Jung et al. This is an open access article