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Báo cáo hóa học: " Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2006 Article ID 98045 Pages 1-11 DOI 10.1155 ES 2006 98045 Rapid Energy Estimation for Hardware-Software Codesign Using FPGAs Jingzhao Ou1 and Viktor K. Prasanna2 1 DSP Design Tools and Methodologies Group Xilinx Inc. San Jose CA 95124 USA 2 Veterbi School of Engineering University of Southern California Los Angeles CA 90089 USA Received 1 January 2006 Revised 25 May 2006 Accepted 19 June 2006 By allowing parts of the applications to be executed either on soft processors as software programs or on customized hardware peripherals attached to the processors FPGAs have made traditional energy estimation techniques inefficient for evaluating various design tradeoffs. In this paper we propose a high-level simulation-based two-step rapid energy estimation technique for hardware-software codesign using FPGAs. In the first step a high-level hardware-software cosimulation technique is applied to simulate both the hardware and software components of the target application. High-level simulation results of both software programs running on the processors and the customized hardware peripherals are gathered during the cosimulation process. In the second step the high-level simulation results of the customized hardware peripherals are used to estimate the switching activities of their corresponding register-transfer gate level low-level implementations. We use this information to employ an instruction-level energy estimation technique and a domain-specific energy performance modeling technique to estimate the energy dissipation of the complete application. A Matlab Simulink-based implementation of our approach and two numerical computation applications show that the proposed energy estimation technique can achieve more than 6000x speedup over low-level simulation-based techniques while sacrificing less than 10 estimation accuracy. Compared with the measured results our experimental results show that the .