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Báo cáo hóa học: " Scalable IC Platform for Smart Cameras"

Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Scalable IC Platform for Smart Cameras | EURASIP Journal on Applied Signal Processing 2005 13 2018-2025 2005 Hindawi Publishing Corporation Scalable IC Platform for Smart Cameras Richard P. Kleihorst Philips Research Laboratories Professor Holstlaan 4 5656 AA Eindhoven The Netherlands Email richard.kleihorst@philips.com Anteneh A. Abbo Philips Research Laboratories Professor Holstlaan 4 5656 AA Eindhoven The Netherlands Email anteneh.a.abbo@philips.com Vishal Choudhary Philips Research Laboratories Professor Holstlaan 4 5656 AA Eindhoven The Netherlands Email vishal.choudhary@philips.com Harry Broers Philips Industrial Vision P O.Box 218 5600 MD Eindhoven The Netherlands Email harry.broers@philips.com Received 19 December 2003 Revised 24 January 2005 Smart cameras are among the emerging new fields of electronics. The points of interest are in the application areas software and IC development. In order to reduce cost it is worthwhile to invest in a single architecture that can be scaled for the various application areas in performance and resulting power consumption . In this paper we show that the combination of an SIMD singleinstruction multiple-data processor and a general-purpose DSP is very advantageous for the image processing tasks encountered in smart cameras. While the SIMD processor gives the very high performance necessary by exploiting the inherent data parallelism found in the pixel crunching part of the algorithms the DSP offers a friendly approach to the more complex tasks. The paper continues to motivate that SIMD processors have very convenient scaling properties in silicon making the complete SIMD-DSP architecture suitable for different application areas without changing the software suite. Analysis of the changes in power consumption due to scaling shows that for typical image processing tasks it is beneficial to scale the SIMD processor to use the maximum level of parallelism available in the algorithm if the IC supply voltage can be lowered. If silicon cost is of importance the .