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78 Rapid Design and Prototyping of DSP Systems

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We describe a RASSP-based design methodology for application specific signal processing systems which supports reengineering and upgrading of legacy systems using a virtual prototyping design process. | T. Egolf et. Al. Rapid Design and Prototyping of DSP Systems. 2000 CRC Press LLC. http www.engnetbase.com . Rapid Design and Prototyping of DSP Systems 78.1 Introduction 78.2 Survey of Previous Research 78.3 Infrastructure Criteria for the Design Flow 78.4 The Executable Requirement An Executable Requirements Example MPEG-1 Decoder 78.5 The Executable Specification An Executable Specification Example MPEG-1 Decoder 78.6 Data and Control Flow Modeling Data and Control Flow Example 78.7 Architectural Design Cost Models Architectural Design Model 78.8 Performance Modeling and Architecture Verification A Performance Modeling Example SCI Networks Deterministic Performance Analysis for SCI DSP Design Case Single Sensor Multiple Processor SSMP T. Egolf M. Pettigrew J. Debardelaben R. Hezar S. Famorzadeh A. Kavipurapu M. Khan Lan-Rong Dung K. Balemarthy N. Desai Yong-kyu Jung and V. Madisetti 78.9 Fully Functional and Interface Modeling and Hardware Virtual Prototypes Design Example I O Processor for Handling MPEG Data Stream 78.10 Support for Legacy Systems 78.11 Conclusions Acknowledgments Georgia Institute of Technology References The Rapid Prototyping of Application-Specific Signal Processors RASSP 1 2 3 program of the U.S. Department of Defense ARPA and Tri-Services targets a 4X improvement in the design prototyping manufacturing and support processes relative to current practice . Based on a current practice study 1993 4 the prototyping time from system requirements definition to production and deployment of multiboard signal processors is between 37 and 73 months. Out of this time 25 to 49 months are devoted to detailed hardware software HW SW design and integration with 10 to 24 months devoted to the latter task of integration . With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW SW components at multiple abstractions reduction in design time has been shown especially in the area of hardware software .