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Xilinx VHDL Test Bench Tutorial

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This tutorial will guide you through the process of creating a test bench for your VHDL designs, which will aid you in debugging your design before or in addition going to the FPGA for execution. For the sake of simplicity, we will revisit the counter tutorial available at Professor Duckworth’s website: http://ece.wpi.edu/~rjduck/Nexys2%20ISE%2010_1%20Counter%20Tutorial.pdf. We will recreate the sample counter and decoder and then create a VHDL test bench for the counter to show what it looks like in the new Xilinx software. This process will be helpful to you in the later labs in the course, as you will be able.