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DSP phòng thí nghiệm thử nghiệm bằng cách sử dụng C và DSK TMS320C31 (P2)

Architecture and Instruction Set of the TMS320C3x Processor Architecture and Instruction set of the TMS320C3x processor Memory addressing modes Assembler directives Programming examples using TMS320C3x assembly code, C code, and C-callable TMS320C3x assembly function. Several programming examples included in this chapter illustrate the architecture, the assembler directives, and the instruction set of the TMS320C3x processor and associated tools. | Digital Signal Processing Laboratory Experiments Using C and the TMS320C31 DSK Rulph Chassaing Copyright 1999 John Wiley Sons Inc. Print ISBN 0-471-29362-8 Electronic ISBN 0-471-20065-4 2 Architecture and Instruction Set of the TMS320C3x Processor Architecture and Instruction set of the TMS320C3x processor Memory addressing modes Assembler directives Programming examples using TMS320C3x assembly code C code and C-callable TMS320C3x assembly function. Several programming examples included in this chapter illustrate the architecture the assembler directives and the instruction set of the TMS320C3x processor and associated tools. 2.1 INTRODUCTION Texas Instruments Inc. introduced the first-generation TMS32010 digital signal processor in 1982 the second-generation TMS32020 in 1985 followed by the C-MOS version TMS320C25 in 1986 1-5 and the TMS320C50 in 1991. The first-generation processor contains 144 x 16 bits of internal or on-chip memory RAM with a 200-ns instruction cycle time. Most of the instructions can be executed in one instruction cycle. Members of the first-generation of processors are currently available in C-MOS versions with faster execution speeds. The second-generation TMS320C25 contains 544 x 16 bits of on-chip RAM is upward code-compatible with the TMS320C10 C1x family of processors and has an instruction cycle time of 100 ns making it capable of executing 10 million instructions per second MIPS . Other members of the second-generation C2x family of processors are currently available with a faster execution speed. The TMS320C50 processor is code-compatible with the first two generations of C1x and C2x processors. Within the same generation several versions of each of these processors C1x C2x and C5x are available with different features such as a faster execution speed and availability of on-chip 19 20 Architecture and Instruction Set of the TMS320C3x Processor ROM. The C1x C2x and C5x are fixed-point processors based on a modified Harvard .