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Logic Synthesis With Verilog HDL part 1

[ Team LiB ] 14.1 What Is Logic Synthesis? Simply speaking, logic synthesis is the process of converting a high-level description of the design into an optimized gate-level representation, given a standard cell library and certain design constraints. | Team LiB 14.1 What Is Logic Synthesis Simply speaking logic synthesis is the process of converting a high-level description of the design into an optimized gate-level representation given a standard cell library and certain design constraints. A standard cell library can have simple cells such as basic logic gates like and or and nor or macro cells such as adders muxes and special flipflops. A standard cell library is also known as the technology library. It is discussed in detail later in this chapter. Logic synthesis always existed even in the days of schematic gate-level design but it was always done inside the designer s mind. The designer would first understand the architectural description. Then he would consider design constraints such as timing area testability and power. The designer would partition the design into high-level blocks draw them on a piece of paper or a computer terminal and describe the functionality of the circuit. This was the high-level description. Finally each block would be implemented on a hand-drawn schematic using the cells available in the standard cell library. The last step was the most complex process in the design flow and required several time-consuming design iterations before an optimized gate-level representation that met all design constraints was obtained. Thus the designer s mind was used as the logic synthesis tool as illustrated in Figure 14-1. Figure 14-1. Designer s Mind as the Logic Synthesis Tool The advent of computer-aided logic synthesis tools has automated the process of converting the high-level description to logic gates. Instead of trying to perform logic synthesis in their minds designers can now concentrate on the architectural trade-offs high-level description of the design accurate design constraints and optimization of cells in the standard cell library. These are fed to the computer-aided logic synthesis tool which performs several iterations internally and generates the optimized gate-level .