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Logic Synthesis With Verilog HDL part 3

[ Team LiB ] 14.4 Synthesis Design Flow Having understood how basic Verilog constructs are interpreted by the logic synthesis tool, let us now discuss the synthesis design flow from an RTL description to an optimized gate-level description. 14.4.1 RTL to Gates | Team LiB 14.4 Synthesis Design Flow Having understood how basic Verilog constructs are interpreted by the logic synthesis tool let us now discuss the synthesis design flow from an RTL description to an optimized gate-level description. 14.4.1 RTL to Gates To fully utilize the benefits of logic synthesis the designer must first understand the flow from the high-level RTL description to a gate-level netlist. Figure 14-4 explains that flow. Figure 14-4. Logic Synthesis Flow from RTL to Gates Let us discuss each component of the flow in detail. RTL description The designer describes the design at a high level by using RTL constructs. The designer spends time in functional verification to ensure that the RTL description functions correctly. After the functionality is verified the RTL description is input to the logic synthesis tool. Translation The RTL description is converted by the logic synthesis tool to an unoptimized intermediate internal representation. This process is called translation. Translation is relatively simple and uses techniques similar to those discussed in Section 14.3.3 Interpretation of a Few Verilog Constructs. The translator understands the basic primitives and operators in the Verilog RTL description. Design constraints such as area timing and power are not considered in the translation process. At this point the logic synthesis tool does a simple allocation of internal resources. Unoptimized intermediate representation The translation process yields an unoptimized intermediate representation of the design. The design is represented internally by the logic synthesis tool in terms of internal data structures. The unoptimized intermediate representation is incomprehensible to the user. Logic optimization The logic is now optimized to remove redundant logic. Various technology independent boolean logic optimization techniques are used. This process is called logic optimization. It is a very important step in logic synthesis and it yields an .