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Timing and Delay part 2

[ Team LiB ] 10.2 Path Delay Modeling In this section, we discuss various aspects of path delay modeling. In this section, the terms pin and port are used interchangeably. 10.2.1 Specify Blocks A delay between a source (input or inout) | Team LiB 10.2 Path Delay Modeling In this section we discuss various aspects of path delay modeling. In this section the terms pin and port are used interchangeably. 10.2.1 Specify Blocks A delay between a source input or inout pin and a destination output or inout pin of a module is called a module path delay. Path delays are assigned in Verilog within the keywords specify and endspecify. The statements within these keywords constitute a specify block. Specify blocks contain statements to do the following Assign pin-to-pin timing delays across module paths Set up timing checks in the circuits Define specparam constants For the example in Figure 10-3 we can write the module M with pin-to-pin delays using specify blocks as follows Example 10-3 Pin-to-Pin Delay Pin-to-pin delays module M out a b c d output out input a b c d wire e f Specify block with path delay statements specify a out 9 b out 9 c out 11 d out 11 endspecify gate instantiations and a1 e a b and a2 f c d and a3 out e f endmodule The specify block is a separate block in the module and does not appear under any other block such as initial or always. The meaning of the statements within specify blocks needs to be clarified. In the following subsection we analyze the statements that are used inside specify blocks. 10.2.2 Inside Specify Blocks In this section we describe the statements that can be used inside specify blocks. Parallel connection As discussed earlier every path delay statement has a source field and a destination field. In the path delay statements in Example 10-3 a b c and d are in the position of the source field and out is the destination field. A parallel connection is specified by the symbol and is used as shown below. Usage source_field destination_field delay_value In a parallel connection each bit in source field connects to its corresponding bit in the destination field. If the source and the destination fields are vectors they must have the same number of bits otherwise there is a