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Timing and Delay part 3

[ Team LiB ] 10.3 Timing Checks In the earlier sections of this chapter, we discussed how to specify path delays. The purpose of specifying path delays is to simulate the timing of the actual digital circuit with greater accuracy than gate delays. | Team LiB 10.3 Timing Checks In the earlier sections of this chapter we discussed how to specify path delays. The purpose of specifying path delays is to simulate the timing of the actual digital circuit with greater accuracy than gate delays. In this section we describe how to set up timing checks to see if any timing constraints are violated during simulation. Timing verification is particularly important for timing critical high-speed sequential circuits such as microprocessors. System tasks are provided to do timing checks in Verilog. There are many timing check system tasks available in Verilog. We will discuss the three most common timing checksm tasks setup hold and width. All timing checks must be inside the specify blocks only. Optional notifier arguments used in these timing check system tasks are omitted to simplify the discussion. 1 The IEEE Standard Verilog Hardware Description Language document provides additional constraint checks removal recrem timeskew fullskew. Please refer to it for details. Negative input timing constraints can also be specified. 10.3.1 setup and hold Checks setup and hold tasks are used to check the setup and hold constraints for a sequential element in the design. In a sequential element such as an edge-triggered flip-flop the setup time is the minimum time the data must arrive before the active clock edge. The hold time is the minimum time the data cannot change after the active clock edge. Setup and hold times are shown in Figure 10-6. Figure 10-6. Setup and Hold Times setup task Setup checks can be specified with the system task setup. Usage setup data_event reference_event limit data_event Signal that is monitored for violations reference_event Signal that establishes a reference for monitoring the data_event signal limit Minimum time required for setup of data event Violation is reported if Treference event - Tdata event limit. An example of a setup check is shown below. Setup check is set. clock is the reference data is