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Handbook of algorithms for physical design automation part 80

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Handbook of Algorithms for Physical Design Automation part 80 provides a detailed overview of VLSI physical design automation, emphasizing state-of-the-art techniques, trends and improvements that have emerged during the previous decade. After a brief introduction to the modern physical design problem, basic algorithmic techniques, and partitioning, the book discusses significant advances in floorplanning representations and describes recent formulations of the floorplanning problem. The text also addresses issues of placement, net layout and optimization, routing multiple signal nets, manufacturability, physical synthesis, special nets, and designing for specialized technologies. It includes a personal perspective from Ralph Otten as he looks back on. | 772 Handbook of Algorithms for Physical Design Automation FIGURE 37.1 SEM picture showing a bridging fault on Metal 3. Note the row of vias on each metal line. Reprinted from Song Z.G. Neo S.P. Loh S.K. and Oh C.K. International Symposium for Testing and Failure Analysis 2005. With permission. The yield ingredient Tbatch can be further classified based on either type of defect or of failure. A taxonomy of failure types is as follows Catastrophic yield loss. These are functional failures such as open or short circuits that cause the part to not work at all. Extra or missing material particle defects are the primary causes for such failures. Figure 37.1 2 shows a magnified view of a bridging fault. The yield loss due to such faults can be predicted by critical area analysis and this is discussed later in this chapter. Parametric yield loss. These failures occur when the chip is functionally correct but it fails to meet some power or performance criteria. Parametric failures are caused by variations in one or set of circuit parameters such that their specific distribution in a design causes it fall out of specifications. For example a part may function at a certain VDD value but not over entire required range of VDD. Another example of parametric yield loss is due to leakage in deep submicron technologies 3 where parametric failures may be caused by process variations. Some classes of integrated circuits may be speed-binned i.e. grouped by performance a common example of this class of designs is microprocessors wherein lower performance parts are priced lower. Typical ASICs are an example of a class of circuits that cannot be speed-binned because they cannot be sold if their performance is below a certain threshold e.g. due to compliance with standards . For these circuits there can be significant performance-limited yield loss and therefore they are designed with a large guardband. However even in case of speed-binned circuits yield loss is important because there .