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Verilog synthesis methodology

Tham khảo tài liệu 'verilog synthesis methodology', công nghệ thông tin, phần cứng phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 1.0 Verilog Synthesis Methodology Finbarr O Regan finbarr@ee.ucd.ie October 2001 Synthesis is a contraint driven process i.e. the synthesis script needs timing constraints Follow the following methodology for best results 1. Draw a simple block diagram labelling all signals widths etc. 2. Draw a timing diagram with as much detail as possible 3. Code the HDL according to the synthesizable templates 4. Do a quick low effort compile- just to see if it is synthesizable before simulating. Compare this to the block diagram. Look at the inference report count the number of flip flops - is it the same as the number of flip flops in the code. check for latches - did you want them. If not latches are inferred in combinational procedures - the inferrence report tells you which combinational procedure and the name of the latch. Fully specify all variables in all cases to eliminate latches. Check the case statement inferrence. Was it full parallel Check any incomplete event list warnings Check to see if there are any combinational feedback loops typically only after a compile . Combinational feedback loops can be identified by the signal names in the timing loop. Check the schematic - any ports unconnected Check to see if Designware and Ambitware components have been built correctly. Are these the components that you wanted How many did you want Never ignore any warning that the synthesis tool flags. All warnings need to be understood and typically signed off. 5. Simulate and compare with the timing diagram If your design doesn t meet timing by more than 10 of the clock period then go back to the code. If you are within 10 of the clock period then try a different compile strategy. October 18 2001 1 2.0 Synthesizeable Templates 2.1 Combinational Logic Using a reg -------------------------------- wire a b reg c always @ a or b c a b Using a wire -------------------------------- wire a b c assign c a b ỊỊ using a built in primitive without instance name if .