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SystemVerilog Assertions Handbook

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Tham khảo tài liệu 'systemverilog assertions handbook', công nghệ thông tin, phần cứng phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | ii SystemVerilog Assertions Handbook SystemVerilog Assertions Handbook . for Formal and Dynamic Verification Published by VhdlCohen Publishing P.O. 2362 Palos Verdes Peninsula CA 90274-2362 vhdlcohen@aol.com http www.vhdlcohen.com Library of Congress Cataloging-in-Publication Data A C.I.P. Catalog record for this book is available from the Library of Congress SystemVerilog Assertions Handbook . for Formal and Dynamic Verification ISBN 0-9705394-7-9 Copyright 2005 by VhdlCohen Publishing All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means electronic or mechanical including photocopying recording or by any information storage and retrieval system without the prior written permission from the author except for the inclusion of brief quotations in a review. Printed on acid-free paper Printed in the United States of America Preface iii Contents Foreword . xi Surrendra A. Dudani . xi Stuart Sutherland . xiii Harry D. Foster . xv Tarak Parikh . xvii Keith Rieken . . xix Yu-Chin Hsu . . xxi Alain Raynaud . xxiii Preface . xxv Acknowledgements . xxix About the authors . xxxiii Disclaimer . xxxv 1 ROLE OF SYSTEMVERILOG ASSERTIONS IN A VERIFICATION METHODOLOGY . 1 1.1 History of Design Verification methodologies . 2 1.2 SystemVerilog Assertions in verification Strategy . 5 1.2.1 Are Assertions Independent from SystemVerilog Structures . 5 1.2.2 Are Assertions Useful for the Definition and Verification of Designs . 6 1.2.2.1 Captures Designer Intent . 7 1.2.2.2 Allows Protocols to be Defined and Verified. 8 1.2.2.3 Reduces the Time to Market . 8 1.2.2.4 Greatly Simplifies the Verification of Reusable IP . 8 1.2.2.5 Facilitates Functional Coverage Metrics . 9 1.2.2.6 Generates Counterexamples to Demonstrate Violation of Properties . 10 1.2.3 Can should entire functional verification task be performed using SystemVerilog Assertions . 10 1.2.4 Is SystemVerilog Assertions Solely Restricted to Applications that Use .