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MEMORY, MICROPROCESSOR, and ASIC phần 7

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Bước đầu tiên trong hỗ trợ kỹ thuật tĩnh cấp bóng bán dẫn là để phân vùng các mạch vào dc thành phần kết nối (DCCs), cũng được gọi là kênh kết nối các thành phần. DCC là một tập hợp của các nút được kết nối với nhau thông qua các thiết bị đầu cuối nguồn và cống của đại diện bóng bán dẫn cấp transistors. | 9-14 Memory Microprocessor and ASIC 9.8.2 Full-Chip Configuration In this phase the design netlists and libraries are combined with control and specification files and downloaded to program the emulation hardware. In the first stage of configuration the netlists are parsed for semantic analysis and logic optimization.24 The design is then partitioned into a number of logic board modules LBMs in order to satisfy the logic and pin constraints of each LBM. The logic assigned to each LBM is flattened checked for timing and connectivity and further partitioned into clusters to allow the mapping of each cluster to an individual FPGA.25 Finally the interconnections between the LBMs are established and the design is downloaded to the emulator. 9.8.3 Testbed and In-circuit Emulation The testbed is the hardware environment in which the design to be emulated will finally operate. This consists of the target ICE board logic analyzer and supporting laboratory equipment.24 The target ICE board contains PROM sockets I O ports and headers for the logic analyzer probes. Verification takes place in two modes the simulation mode and ICE. In the simulation mode the emulator is operated as a fast simulator. Software is used to simulate the bus master and other hardware devices and the entire simulation test suite is run to validate the emulation model.25 An external monitor and logic analyzer are used to study results at internal nodes and determine success. In the ICE mode the emulator pins are connected to the actual hardware application environment. Initially diagnostic tests are run to verify the hardware interface. Finally application software provides the emulation model with billions of vectors for high-speed functional verification. In Section 9.9 we conclude our discussion on design verification and review some of the areas of current research. 9.9 Conclusion Microprocessor design teams use a combination of simulation and formal verification to verify presilicon designs. .