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MEMORY, MICROPROCESSOR, and ASIC phần 10

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Lấy một LFSR / SR, theo đó mối quan hệ không lệ thuộc giữ cho mỗi D-tập hợp các mạch liên quan đến việc cơ bản là một tìm kiếm một đa thức áp dụng mức độ d, kdn, trong số tất cả các đa thức nguyên thủy của độ d, kd n. Các đa thức nguyên thủy của mức độ nào có thể được tạo ra thuật toán. | 15-12 Memory Microprocessor and ASIC Obtaining an LFSR SR under which the independency relation holds for every D-set of the circuit involves basically a search for an applicable polynomial of degree d k d n among all primitive polynomials of degree d k d n. Primitive polynomials of any degree can be algorithmically generated. An applicable polynomial of degree n is of course bound to exist this corresponds to exhaustive testing but in order to keep the number of test cycles low the degree should be minimized. Built-In Output Responseverification Mechanisms Verification of the output responses of a circuit under a set of test patterns consists in principle of comparing each resulting output value against the correct one which has been precomputed and prestored for each test pattern. However for built-in output response verification such an approach cannot be used at least for large test sets because ofthe associated storage overhead. Rather practical built-in output response verification mechanisms rely on some form of compression of the output responses so that only the final compressed form needs to be compared against the precomputed and prestored compressed form of the correct output response. Some representative built-in output response verification mechanisms based on compression are given below. 1. Ones count In this scheme the number of times that each output of the circuit is set to 1 by the applied test patterns is counted by a binary counter and the final count is compared against the ABCDEF tl 1 10000 101000 3 100100 4 1000 1 0 t5 100001 011000 010100 010010 9 010001 tto 001100 til 001010 l12 00100 I tl3 000 1 1 0 t 4 000 10 1 tIS 0000 1 1 t.6 111111 FIGURE 15.9 A pseudo-exhaustive test set for any circuit with six inputs and largest D-set corresponding count in the fault-free circuit. 2 Transition count In this scheme the number of transitions i.e. changes from both 0 1 and 1 0 that each output of the circuit goes through when the test set is applied .