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distributed operating system phần 6

Tham khảo tài liệu 'distributed operating system phần 6', công nghệ thông tin, đồ họa - thiết kế - flash phục vụ nhu cầu học tập, nghiên cứu và làm việc hiệu quả | 296 DISTRIBUTED SHARED MEMORY CHAP. 6 more than one word multiple bus cycles will be needed to update the entire block. The issue of invalidate vs. update occurs in all cache protocols and also in DSM systems. The complete protocol is summarized in Fig. 6-3. The first column lists the four basic events that can happen. The second one tells what a cache does in response to its own CPU s actions. The third one tells what happens when a cache sees by snooping that a different CPU has had a hit or miss. The only time cache s the snooper must do something is when it sees that another CPU has written a word that s has cached a write hit from S s point of view . The action is for s tojdelete the word from its cache. The write-through protocol is simple to understand and implement but has the serious disadvantage that all writes use the bus. While the protocol certainly reduces bus traffic to some extent the number of CPUs that can be attached to a single bus is still too small to permit large-scale multiprocessors to be built using it. Fortunately for many actual programs once a CPU has written a word that CPU is likely to need the word again and it is unlikely that another CPU will use the word quickly. This situation suggests that if the CPU using the word could somehow be given temporary ownership of the word it could avoid having to update memory on subsequent writes until a different CPU exhibited interest in the word. Such cache protocols exist. Goodman 1983 devised the first one called write once. However this protocol was designed to work with an existing bus and was therefore more complicated than is strictly necessary. Below we will describe a simplified version of it which is typical of all ownership protocols. Other protocols are described and compared by Archibald and Baer 1986 . Our protocol manages cache blocks each of which can be in one of the following three states 1. INVALID This cache block does not contain valid data. 2. CLEAN Memory is up-to-date the