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analog bicmos design practices and pitfalls phần 7

Cascading của các giai đoạn tuần tự có thể được thực hiện mà không cần cho phù hợp với trở kháng, và lợi nhuận tương đối cao có thể được thực hiện trong một khu vực nhỏ của mạch, đặc biệt là khi kết hợp với vô gương hoạt động hiện tại. MOS khác biệt giữa các bộ khuếch đại được gọi là một cặp nguồn-cùng. | chapter 6 Comparators A comparator is a functional circuit block that compares the relative levels of two signals. The comparator s output signal provides a logic 1 or 0 depending on the result of the comparison. The ideal comparator is perfectly accurate and instantly provides the correct output. Again real iife intrudes i jud gives US hmits. Finite gam and non-zero propagation delays result in delays between the input signal being applied and the output signal being available. Input offsets result in errors in the comparison. However theee jrrt ll n s can be overcome and many circuits can be built from the basic comparator. Oscillators d a converters and a d converters all use some form of comparator and operational amplifiers are comparators with frequency compensation. Figure 6.1 A typical comparator input stage. Consider the emitter-coupled pair shown in Figure 6.1. This is a standard comparator input stage. We can use Kirchoff s Voltage Law on the loop starting at V1 s ground and ending at V2 s ground to obtain V1 - Vbe P1 Vbe P2 - V2 0 We can express diode equation the base-emitter voltages of the transistors using the Vbe P 1 Vt ln IS1 Vbe P2 Vt ln IS2 If we assume the pnp transistors are identical then IS1 IS2 and the ratio of collector currents is given as IC- x i f IC2 Vt J VT This circuit acts as a linear amplifier for a small range around Vdif 0. However when Vdif exceeds several tens of millivolts this circuit acts as a pair of complementary switches. We have previously analyzed current mirrors and found that a transistor s collector current approximately doubles for an increase of 18mV in the magnitude of the base-emitter voltage. In the circuit of Figure 6.1 hie total current available is equal to the bias current. When V1 V2 boh I rransĩstors are conducting. If we assume Ị3 is infinite IC1 IC2 Ibias 2. If V1 is 18mV lower than V2 the magnĩtude of Pl s Vbe is 18mV greater than that of P2 and Pl will conduct twice the current that P2 does. Thus IC1 2