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managing power electronics vlsi and dsp driven computer systems nov 2005 phần 9

có ba bộ nhớ cổng kết hợp với mạch 10 cấu hình cổng iega1 ter (. một cổng dữ liệu đăng ký IPORTGD). và một đầu vào cảng đăng ký (1 được sử dụng để cấu hình các chân như các đầu vào hoặc đầu ra PLN có thể đượchông số kỹ thuật Phụ lục | Appendix E Fairchild Specifications for ACE15Ũ2 307 Figure 27. Multi-input Wakeup MIW Block Diagram WKEDG 0 7 WKPND 0 7 10 WKINTEN Bit 7 of TOCNTRL 9. I O Port The eight I O pins SIX on 8-pin package option are bidirectional see Figure 28 . The bi-directional I O pins can be individually configured by software to operate as high-impedance inputs as inputs with weak pull-up. or as push-pull outputs. The operating state is determined by the contents of the corresponding bits in the data and configuration registers. Each bi-directional I O pin can be used for general purpose I O or in some cases for a specific alternate function determined by the on-chip hardware. Figure 28. PORTGD Logic Diagram GXPULLEN GXBUFEN GXOUT 9.1 I O registers The I O pins G0-G7 have three memory-mapped port registers associated with the I O circuitry a port configuration register PORTGC a port data register PORTGD and a port input register PORTGP . PORTGC is used to configure the pins as inputs or outputs. A pin may be configured as an input by writing a 0 or as an output by writing a 1 to its corresponding PORTGC bit. ft a pin IS configured as an output its PORTGD bit represents the state of the pin 1 logic high 0 logic low . If the pin is configured as an input its PORTGD bit selects whether the pin IS a weak pull-up or a high-impedance input. Table 13 provides details of the port configuration options. The port configuration and data registers can both be read from or written to. Reading PORTGP returns the value of the port pins regardless of how the pins are configured. Since this device supports MIW PORTG inputs have Schmitt triggers. Figure 29. I O Register bit assignments PORTGC PORTGD PORTGD Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bito 1G7 G6 G5 G4 2G3 G2 G1 GO Table 13. I O configuration options Configuration Bit Data Bit Port Pin Configuration 0 0 High-impedence input TRI-STATE input 0 1 Input with pull-up weak one input 1 0 Push-pull zero output 1 1 Push-pull one output _ _ _ _