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Digital logic testing and simulation phần 6

Khi D1 và D2 hội tụ tại đầu ra của cổng 8, nếu nó được tìm thấy rằng các đầu vào trên đến cổng 14 đã được thử nghiệm, sau đó D1 có thể được thanh lọc bằng cách chỉ định một từ 0 đến đầu vào trên cổng 8. Khi xung đột xảy ra, độ phân giải của nó thường đòi hỏi phải phân đoạn của chuỗi Di bị xóa. AALG hoàn thành điều này với các chức năng | A TESTBENCH 327 In this chapter fault simulation and ATPG will be examined from the user s perspective. What kind of reports should be generated and how do test programs get translated into tester format Users have in the past been quite critical of fault simulators complaining that they simply produced a fault coverage number based on the test vectors and the fault list without producing any meaningful suggestions help or insight into how to improve on that number. We will examine ways in which fault simulation results can be made more meaningful to the end user. The workflow depicted in Figure 7.2 is quite general it could describe almost any design project. The circuit being designed may be constrained by rigid design rules or it may be free form with the logic designers permitted complete freedom in how they go about implementing their design. However as details get more specific e.g. is the design synchronous or asynchronous choices start becoming bounded. Many of the vexing problems related to testing complex sequential circuits will be postponed to subsequent chapters where we address the issue of design-for-testability DFT . For now the focus will be on the fault simulator and the ATPG and how their interactions can be leveraged to produce a test program that is thorough while at the same time brief. 7.4 A TESTBENCH A testbench will be created for the circuit in Figure 7.3 using Verilog. A VHDL description at the structural level would be quite similar and the reader who understands the following discussion should have no difficulty understanding an equivalent VHDL description of this circuit. The testbench instantiates two modules the first is the circuit description while the second contains the test stimuli including timing data. The circuit description is hierarchical containing modules for a mux and a flip-flop. The test stimulus module follows the hierarchical netlist testbench. 7.4.1 The Circuit Description The Verilog circuit description that .