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Introducing the MC68HC12

Like any truly general purpose microcontroller, the new MC68HC12 family is going to mean a lot of different things to a lot of different users. | Introducing the MC68HC12 part 1 of 3 James M. Sibigtroth Mail drop OE313 Motorola AMCU 6501 William Cannon Dr W Austin TX 78735-8598 RFTP70@email.sps.mot.com Like any truly general purpose microcontroller the new MC68HC12 family is going to mean a lot of different things to a lot of different users. To developers of battery operated applications the 68HC12 will mean low voltage 2.7 volts and low power consumption. To 68HC11 users it will mean a much higher performance MCU with a rich superset of HC11 instructions. To developers of larger programs written in C the 68HC12 will mean very efficient high-level language programs and easy access to more than 4 megabytes of program space. And everyone will like the new single-wire background debug mode. This article describes the overall features of the first two derivatives of this family and compares the CPU12 to the M68HC11 CPU. Subsequent articles in this series will provide greater detial on some of the most interesting new features of this new MCU family. The Seeds of a New Generation of MCUs The first M68HC12 device to reach silicon was the 112-pin MC68HC812A4 which is primarily intended for larger expanded mode systems. The second device the 80-pin MC68HC912B32 is intended primarily for single-chip applications. Both devices are based on a modular layout and the new 16-bit CPU12 processor which is completely compatible with M68HC11 programs but it is greatly enhanced. The silicon process is designed to operate at 8MHz bus speed over the whole supply range from 2.7 to 5.5 volts and low power design techniques were emphasized throuout the chip. The most significant difference between the first two derivatives is the expansion bus structure and the on-chip memory. The MC68HC812A4 has 1k bytes of static RAM and 4k bytes of byte-erasable EEPROM but no large program memory. Systems based on this MCU use a non-multiplexed bus to access external program memory. Up to 22 address lines plus 6 programmable chip selects allow