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Lecture Introduction to computing systems (2/e): Chapter 5 - Yale N. Patt, Sanjay J. Patel

Chapter 5 - The LC-3. This chapter presents the following content: The ISA: overview, operate instructions, data movement instructions, control instructions, another example: counting occurrences of a character, the data path revisited. | Chapter 5 The LC-2 Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). 5- LC-2 Overview: Memory and Registers Memory address space: 216 locations (16-bit addresses) addressibility: 16 bits Registers temporary storage, accessed in a single machine cycle accessing memory generally takes longer than a single cycle eight general-purpose registers: R0 - R7 each 16 bits wide how many bits to uniquely identify a register? other registers not directly addressible, but used by (and affected by) instructions PC (program counter), condition codes 5- LC-2 Overview: Instruction Set Opcodes 16 opcodes Operate instructions: ADD, AND, NOT Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI Control instructions: BR, JSR, JSRR, RET, RTI, TRAP some opcodes set/clear condition codes, based on result: N = negative, Z = zero, P = positive (> 0) Data Types 16-bit 2’s complement integer Addressing Modes How is the location of an operand specified? non-memory addresses: immediate, register memory addresses: direct, indirect, base+offset 5- Operate Instructions Only three operations: ADD, AND, NOT Source and destination operands are registers These instructions do not reference memory. ADD and AND can use “immediate” mode, where one operand is hard-wired into the instruction. Will show dataflow diagram with each instruction. illustrates when and where data moves to accomplish the desired operation 5- NOT (Register) Note: Src and Dst could be the same register. 5- ADD/AND (Register) this zero means “register mode” 5- ADD/AND | Chapter 5 The LC-2 Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). 5- LC-2 Overview: Memory and Registers Memory address space: 216 locations (16-bit addresses) addressibility: 16 bits Registers temporary storage, accessed in a single machine cycle accessing memory generally takes longer than a single cycle eight general-purpose registers: R0 - R7 each 16 bits wide how many bits to uniquely identify a register? other registers not directly addressible, but used by (and affected by) instructions PC (program counter), condition codes 5- LC-2