Đang chuẩn bị liên kết để tải về tài liệu:
Basic Concepts part 2

[ Team LiB ] 3.2 Data Types This section discusses the data types used in Verilog. 3.2.1 Value Set Verilog supports four values and eight strengths to model the functionality of real hardware. The four value levels are listed in Table 3-1. Table 3-1. | Team LiB 3.2 Data Types This section discusses the data types used in Verilog. 3.2.1 Value Set Verilog supports four values and eight strengths to model the functionality of real hardware. The four value levels are listed in Table 3-1. Table 3-1. Value Levels Value Level Condition in Hardware Circuits 0 Logic zero false condition 1 Logic one true condition x Unknown logic value z High impedance floating state In addition to logic values strength levels are often used to resolve conflicts between drivers of different strengths in digital circuits. Value levels 0 and 1 can have the strength levels listed in Table 3-2. Table 3-2. Strength Levels Strength Level Type Degree supply Driving strongest strong Driving pull Driving large Storage weak Driving medium Storage small Storage highz High Impedance weakest If two signals of unequal strengths are driven on a wire the stronger signal prevails. For example if two signals of strength strongl and weakO contend the result is resolved as a strongl. If two signals of equal strengths are driven on a wire the result is unknown. If two signals of strength strongl and strongO conflict the result is an x. Strength levels are particularly useful for accurate modeling of signal contention MOS devices dynamic MOS and other low-level devices. Only trireg nets can have storage strengths large medium and small. Detailed information about strength modeling is provided in Appendix A Strength Modeling and Advanced Net Definitions. 3.2.2 Nets Nets represent connections between hardware elements. Just as in real circuits nets have values continuously driven on them by the outputs of devices that they are connected to. In Figure 3-1 net a is connected to the output of and gate gl. Net a will continuously assume the value computed at the output of gate gl which is b c. Figure 3-1. Example of Nets Nets are declared primarily with the keyword wire. Nets are one-bit values by default unless they are declared explicitly as vectors. The terms .