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Gate Level Modeling part 1

[ Team LiB ] 5.1 Gate Types A logic circuit can be designed by use of logic gates. Verilog supports basic logic gates as predefined primitives. These primitives are instantiated like modules except that they are predefined in Verilog and do not need a module definition. | Team LiB 5.1 Gate Types A logic circuit can be designed by use of logic gates. Verilog supports basic logic gates as predefined primitives. These primitives are instantiated like modules except that they are predefined in Verilog and do not need a module definition. All logic circuits can be designed by using basic gates. There are two classes of basic gates and or gates and buf not gates. 5.1.1 And Or Gates And or gates have one scalar output and multiple scalar inputs. The first terminal in the list of gate terminals is an output and the other terminals are inputs. The output of a gate is evaluated as soon as one of the inputs changes. The and or gates available in Verilog are shown below. and or xor nand nor xnor The corresponding logic symbols for these gates are shown in Figure 5-1. We consider gates with two inputs. The output terminal is denoted by out. Input terminals are denoted by i1 and i2. Figure 5-1. Basic Gates These gates are instantiated to build logic circuits in Verilog. Examples of gate instantiations are shown below. In Example 5-1 for all instances OUT is connected to the output out and IN 1 and IN2 are connected to the two inputs i1 and i2 of the gate primitives. Note that the instance name does not need to be specified for primitives. This lets the designer instantiate hundreds of gates without giving them a name. More than two inputs can be specified in a gate instantiation. Gates with more than two inputs are instantiated by simply adding more input ports in the gate instantiation see Example 5-1 . Verilog automatically instantiates the appropriate gate. Example 5-1 Gate Instantiation of And Or Gates wire OUT IN1 IN2 basic gate instantiations. and a1 OUT IN1 IN2 nand na1 OUT IN1 IN2 or or1 OUT IN1 IN2 nor nor1 OUT IN1 IN2 xor x1 OUT IN1 IN2 xnor nx1 OUT IN1 IN2 More than two inputs 3 input nand gate nand na1_3inp OUT IN1 IN2 IN3 gate instantiation without instance name and OUT IN1 IN2 legal gate instantiation The truth tables for these .