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Chapter 8: Advanced Design Techniques and Recent Design Examples of CMOS OP AMPs

Tài liệu tham khảo về bài tập lớn vi điện tử. | 8 - 1 CHUNG-YU WU Chapter 8 Advanced Design Techniques and Recent Design Examples of CMOS OP AMPs 8-1 Advanced Design Techniques of CMOS OP AMPs 8-1.1 Improved PSRR and frequency compensation P626 l C dlo 1 dVGSi Cgd 1 dlo . - Vss C _dVss -g Vss J C 2g dVss dVout Cgd 1 _ Io 1 Cgs 1 Io dVDD C dVDD 2gm. J Cj 2gm1 dVDD Where Io represents the input stage bias current. If Io is independent of Vss and VDD and the input devices have no body effect. 0 - V 3Vdd Ci Ref. IEEE JSSC vol. SC-15 pp.929-938 Dec. 1980 IREF is generated by using the power supply independent current source. VBIAS is nearly independent of VDD and Vss. It is better to use separate p-wells for M1 and M2 to avoid the body effect. Tracking RC compensation Conceptual circuits 8 - 2 CHUNG-YU WU In the quiescent case Vin2 Vos2 Cc If W L a W L b W L c Kr-C -Cc CL RdsA Cc Cl ------L Rc gm 2Cc The requires Rc is Rc 1 gm2 1 Cd CL Cc 1 gm2 Cc CL Cc Thus LHP zero LHP pole P2 and P3 becomes the second pole. The stability considerations P3 AdP or Cc gm c1cL gm 2 allows a smaller gm2 and larger CL RdsA Rc indep of temperature process and supply variations. Tracking design to make sure that z P2 No pole-zero doublet problem 8 - 3 CMOS Design CHUNG-YU WU M17 Cc Tracking RC compensation. M9 M11 Sharing the separate n-well. VBiaS is not strictly independent of VDd and VSS. 8-1.2 Improved frequency compensation technique. Ref. IEEE JSSC vol.sc-18 pp 629-633 Dec.1983 Grounded gate cascode compensation Vdd M11 VBIAS1 Cc 5pF 3x MB M7 BIAS2 Vo M6 I M10 3x VBIAS1 .