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The VHDL Cookbook phần 3

Một số ví dụ về các báo cáo trường hợp: trường hợp element_colour khi màu đỏ = báo cáo cho màu đỏ, khi màu xanh lá cây | xanh = báo cáo cho màu xanh lá cây hoặc màu xanh, khi cam đến màu ngọc lam = báo cáo cho các màu sắc, kết thúc vụ án; opcode trường hợp khi X "00" = perform_add; khi X "01" = perform_subtract; khi những người khác = signal_illegal_opcode, kết thúc vụ án; | 2-12 The VHDL Cookbook Some examples of case statements case element_colour of when red statements for red when green blue statements for green or blue when orange to turquoise statements for these colours end case case opcode of when X 00 perform_add when X 01 perform_subtract when others signal_illegal_opcode end case 2.4.4. Loop Statements VHDL has a basic loop statement which can be augmented to form the usual while and for loops seen in other programming languages. The syntax of the loop statement is loop_statement 7oop_label iteration_scheme loop sequence_of_statements end loop loop_label iteration_scheme while condition for 7oop_parameter_specification parameter_specification identifier in discrete_range If the iteration scheme is omitted we get a loop which will repeat the enclosed statements indefinitely. An example of such a basic loop is loop do_something end loop The while iteration scheme allows a test condition to be evaluated before each iteration. The iteration only proceeds if the test evaluates to true. If the test is false the loop statement terminates. An example while index length and str index loop index index 1 end loop The for iteration scheme allows a specified number of iterations. The loop parameter specification declares an object which takes on successive values from the given range for each iteration of the loop. Within the statements enclosed in the loop the object is treated as a constant and so may not be assigned to. The object does not exist beyond execution of the loop statement. An example for item in 1 to last_item loop table item 0 end loop There are two additional statements which can be used inside a loop to modify the basic pattern of iteration. The next statement terminates execution of the current iteration and starts the subsequent iteration. The 2. VHDL is Like a Programming Language 2-13 exit statement terminates execution of the current iteration and terminates the loop. The syntax of these statements is .