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High Speed USB Platform Design Guidelines

Intel từ chối tất cả trách nhiệm, bao gồm cả trách nhiệm đối với hành vi xâm phạm bất kỳ quyền sở hữu, liên quan đến sử dụng thông tin trong đặc tả này Không có giấy phép, thể hiện hay ngụ ý, bởi le để bác đơn hoặc nếu không, bất kỳ quyền sở hữu trí tuệ được công nhận ở đây. Intel không chịu trách nhiệm cho bất kỳ lỗi nào, mà có thể xuất hiện trong tài liệu này. | iniel. High Speed USB Platform Design Guidelines Rev. 1.0 High Speed USB Platform Design Guidelines REVISION HISTORY Revision Revision History Date 0.9 Preliminary release. 07 12 2000 THIS SPECIFICATION DOCUMENT IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER including any warranty of merchantability NONINFRINGEMENT FITNESS FOR ANY PARTICULAR PURPOSE OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL SPECIFICATION OR SAMPLE. Intel disclaims all liability including liability for infringement of any proprietary rights relating to use of information in this specification. No license express or implied by estoppel or otherwise to any intellectual property rights is granted herein. Intel assumes no responsibility for any errors which may appear in this document. Intel makes no commitment to update the information contained herein and may make changes at any time without notice. Copyright 2000-01 Intel Corporation. All rights reserved. Third-party brands and names are the property of their respective owners. Other product and corporate names may be trademarks of other companies and are only for explanation ant to the owners benefit without intent to infringe. Page 2 4 26 01 High Speed USB Platform Design Guidelines Table of Contents 1 Introduction 4 1.1 Background 4 2 Terminology 5 3 Layout Guidelines 5 3.1 General Routing and Placement 6 3.2 High Speed USB Trace Spacing6 3.3 High Speed USB Termination__7 3.4 High Speed USB Trace Length Matching 7 3.5 High Speed USB Trace Length Guidelines 7 3.6 Plane Splits Voids and Cut-Outs Anti-Etch __7 3.7 Layer Stacking 8 3.8 Component Placement8 4.1 Stubs 2 9 4.2 Poor Routing Techniques 9 5 EMI ESD Considerations 10 5.1 EMI - Common Mode Chokes10 5.2 .