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ARM System Developer’s Guide phần 6

Trường hợp 1: method_1 trở lại (), trường hợp 2: trở về method_2 (), trường hợp 3: trở lại method_3 (); trường hợp 4: trở lại method_4 () Trường hợp 5: trở lại method_5 (); trường hợp 6: trở lại method_6 (); trường hợp 7 : trở lại method_7 (); mặc định: trở lại method_d ();}} | 338 Chapter 9 Exception and Interrupt Handling required the handler may take several actions reenabling interrupts and or performing a context switch. Reenabling interrupts involves switching out of IRQ mode to either SVC or system mode. Interrupts cannot simply be reenabled when in IRQ mode because this would lead to possible link register r14_irq corruption especially if an interrupt occurred after the execution of a BL instruction. This problem will be discussed in more detail in Section 9.3.3. Performing a context switch involves flattening emptying the IRQ stack because the handler does not perform a context switch while there is data on the IRQ stack. All registers saved on the IRQ stack must be transferred to the task s stack typically on the SVC stack. The remaining registers must then be saved on the task stack. They are transferred to a reserved block of memory on the stack called a stack frame. Example This nested interrupt handler example is based on the flow diagram in Figure 9.9. The rest 9.9 of this section will walk through the handler and describe in detail the various stages. Maskmd SVC32md I_Bit EQU 0x1f EQU 0x13 EQU 0x80 FRAME_R0 EQU 0x00 FRAME_R1 EQU FRAME_R0 4 FRAME_R2 EQU FRAME_R1 4 FRAME_R3 EQU FRAME_R2 4 FRAME_R4 EQU FRAME_R3 4 FRAME_R5 EQU FRAME_R4 4 FRAME_R6 EQU FRAME_R5 4 FRAME_R7 EQU FRAME_R6 4 FRAME_R8 EQU FRAME_R7 4 FRAME_R9 EQU FRAME_R8 4 FRAME_R10 EQU FRAME_R9 4 FRAME_R11 EQU FRAME_R10 4 FRAME_R12 EQU FRAME_R11 4 FRAME_PSR EQU FRAME_R12 4 FRAME_LR EQU FRAME_PSR 4 FRAME_PC EQU FRAME_LR 4 FRAME_SIZE EQU FRAME_PC 4 IRQ_Entry instruction SUB r14 r14 4 STMDB r13 r0-r3 r12 r14 service interrupt BL read_RescheduleFlag processor mode mask SVC mode IRQ bit state comment 2 2 save context 3 more processing 9.3 Interrupt Handling Schemes 339 CMP r0 0 3 if processing LDMNEIA r13 r0-r3 r12 pc 4 else return MRS r2 spsr 5 copy spsr_irq MOV r0 r13 5 copy r13_irq ADD r13 r13 6 4 5 reset stack MRS r1 cpsr 6 copy cpsr BIC r1 r1 Maskmd 6 ORR r1 r1 .