Đang chuẩn bị liên kết để tải về tài liệu:
Fundamentals of Digital Electronics - Lab 4

Memory: The D-Latch Trong ba phòng thí nghiệm đầu tiên trong loạt bài này, tất cả các công việc của bạn có được với mạch tổ hợp, trong đó đầu vào trạng thái hoàn toàn xác định trạng thái đầu ra. Trong các mạch vậy, đến nay, không phụ thuộc vào lịch sử quá khứ hoặc làm thế nào bạn đến trạng thái hiện tại. Điều này có nghĩa là "nhớ" không thể được xây dựng vào các mạch. Hầu hết các hoạt động kỹ thuật số tuần tự, trong đó B sự kiện phải xảy ra sau sự. | Lab 4 Memory The D-Latch In the first three labs in this series all your work has been with combinational circuits in which the input states completely determine the output states. In the circuits thus far there is no dependence on past history or how you arrived at the current state. This means that remembering cannot be built into the circuits. Most digital operations are sequential in that event B must occur after event A. Furthermore in a digital computer events are not only sequential but also synchronous with some external clock. Clocked logic devices are devices whose output changes only when a clock signal is asserted. In the next few labs you will see how the addition of clocked logic devices brings memory into digital circuits making it possible to construct many interesting digital circuits. One simple memory circuit is called the data latch or D-latch. This is a device which when told to do so via the clock input notes the state of its input and holds that state at its output. The output state remains unchanged even if the input state changes until another update request is received. Traditionally the input of the D-latch is designated by D and the latched output by Q. The update command is provided by asserting the clock input in the form of a transition from HI to LO or from LO to HI so-called edge-triggered devices or level triggered devices where the output follows the input whenever the clock is HI. National Instruments Corporation 4-1 Fundamentals of Digital Electronics Lab 4 Memory The D-Latch PreSet Xi D QQ Set Clr QQ D Q X 0 01 00 disallowed X 1 10 01 10 10 01 Clock Q clocked logic 11 clocked 1 Clr Figure 4-1. D-Latch Symbol and Truth Tables Data present on the input D is passed to the outputs Q and Q when the clock is asserted. The truth table for an edge-triggered D-latch is shown to the right of the schematic symbol. Some D-latches also have Preset and Clear inputs that allow the output to be set HI or LO independent of the clock signal. In