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Fundamentals of Digital Electronics - Lab 6

JK Master-Slave Flip-Flop Một trong các thiết bị logic quan trọng nhất tốc độ master-slave JK flip-flop. Không giống như các chốt D, chỉ có bộ nhớ cho đến khi một xung đồng hồ đến cùng, các JK flip flop có bộ nhớ đúng. Khi các yếu tố đầu vào J và K thấp, trạng thái của các kết quả đầu ra Q và Q không thay đổi trên clocking. Như vậy, thông tin có thể được đặt vào các bit đầu ra và giữ cho đến khi yêu cầu tại một thời điểm trong tương lai. Sản lượng. | Lab 6 JK Master-Slave Flip-Flop One of the most important clocked logic devices is the master-slave JK flip-flop. Unlike the D-latch which has memory only until another clock pulse comes along the JK flip-flop has true memory. When the J and K inputs are low the state of the outputs Q and Q are unchanged on clocking. Thus information can be placed onto the output bit and held until requested at a future time. The output Q can be clocked low or high by setting the J K inputs to 0 1 or 1 0 respectively. In fact placing an inverter between J and K inputs results in a D-latch circuit. The schematic diagram for the JK flip-flop and its truth table is shown below. Note that the JK flip-flop can also be Set or Reset with direct logic inputs. Set à clock J K Q Q Set Clr QQ J Q _TL 0 0 no change 0 0 disallowed _TL 0 1 0 1 0 1 10 clk Q _TL 1 0 1 0 1 0 01 K _TL 1 1 toggle 1 1 clocked Ỳ Clr clocked logic direct logic Figure 6-1. JK Flip-Flop Logic Symbol and Truth Tables The first entry of the clocked truth table is the memory state while the next two combinations are the latched states. What is new with the JK flip-flop is the fourth combination 1 1 which produces a toggle state. On clocking the output changes from 1-- 0 if 1 or 0-- 1 if 0. This complement function is often referred to as bit toggling and the resulting flip-flop J and K inputs pulled HI is called a T flip-flop. Because only one toggle occurs per output cycle it takes two clock cycles to return the output state to its initial state. Load Binaryl.vi and observe the operation of the T-flip-flop on clocking. National Instruments Corporation 6-1 Fundamentals of Digital Electronics Lab 6 JK Master-Slave Flip-Flop Figure 6-2. LabVIEW Simulation of a Divide-by-Two Counter Using a T Flip-Flop SubVI Each time the Run button is pressed the clock changes state from HI-LO or LO-HI. How many times do you need to press the Run button to cycle the output bit from LO-Hi-LO It may be easier to make the correct observation by .