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Lecture RTL hardware design: Chapter 10 - P. Chu

Chapter 10 covers finite state machine (FSM), which is a sequential circuit with “random” transition patterns. The representation, timing and implementation issues of FSMs are studied with an emphasis on its use as the control circuit for a large, complex system. | Finite State Machine RTL Hardware Design by P. Chu Chapter 10 1 Outline 1. 2. 3. 4. 5. 6. 7. 8. Overview FSM representation Timing and performance of an FSM Moore machine versus Mealy machine VHDL description of FSMs State assignment Moore output buffering FSM design examples RTL Hardware Design by P. Chu Chapter 10 2 1. Overview on FSM • Contain “random” logic in next-state logic • Used mainly used as a controller in a large system • Mealy vs Moore output RTL Hardware Design by P. Chu Chapter 10 3 2. Representation of FSM • State diagram RTL Hardware Design by P. Chu Chapter 10 4 • E.g. a memory controller RTL Hardware Design by P. Chu Chapter .