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VHDL Programming by Example phần 9

Chính xác thời gian hỗ trợ kiểm tra-Kiểm tra bao gồm kiểm tra thiết lập, tổ chức kiểm tra, kiểm tra pulsewidth, kiểm tra thời gian, và phát hiện lỗi chính xác. Nhiều cách để xác định chức năng, tính năng có thể được quy định cụ thể với các bảng sự thật, bảng nhà nước, nguyên thủy boolean, hoặc mô tả một hành vi. | 382 Chapter Seventeen Accurate timing check support Checks include setup checks hold checks pulsewidth checks period checks and accurate glitch detection. Many ways to specify functionality Functionality can be specified with truth tables state tables boolean primitives or a behavioral description. All of these features give the designer the ability to create timing-accurate FPGA or ASIC libraries. VITAL Simulation Process Overview The place and route tool generates a number of output files as we saw in the last chapter. The VITAL simulation uses two of these files. The first is the VHDL netlist. This is a file containing component declarations signals and component instantiations that connect all of the components together with the declared signals to form the functionality of the design. This file is read by the VITAL simulator and used to create the component connectivity in the database. The second file is an SDF Standard Delay Format file that describes the timing for the design. For each instance in the netlist this file contains SDF statements that describe the delays and timing checks for the instance. This information is used during simulation to model the timing behavior. To build the VITAL simulation database the simulator needs to have a VITAL library that contains components for the target technology and the VHDL netlist and SDF timing file from the place and route tools. The simulator uses the netlist to instantiate the proper instances from the VITAL library in the internal database and then apply timing to the instances with the SDF file. Each of the instances contains a number of generics that receive the timing information. The timing data is used within the model to provide the correct behavior of the underlying device. VITAL Implementation VITAL descriptions follow a standard style and make use of standard functions and procedures from two VITAL packages. The VITAL Timing CPU Vital Simulation 383 Package contains procedures and functions for .