The truth tables for these gates are very simple. Truth tables for gates with one input and one output are shown in Table 5-2. Table 5-2. Truth Tables for Buf/Not Gates | The truth tables for these gates are very simple. Truth tables for gates with one input and one output are shown in Table 5-2. Table 5-2. Truth Tables for Buf Not Gates Bufif notif Gates with an additional control signal on buf and not gates are also available. bufif1 notif1 bufif0 notif0 These gates propagate only if their control signal is asserted. They propagate z if their control signal is deasserted. Symbols for bufif notif are shown in Figure 5-3. Figure 5-3. Gates Bufif and Notif The truth tables for these gates are shown in Table 5-3. Table 5-3. Truth Tables for Bufif Notif Gates These gates are used when a signal is to be driven only when the control signal is asserted. Such a situation is applicable when multiple drivers drive the signal. These drivers are designed to drive the signal on mutually exclusive control signals. Example 5-3 shows examples of instantiation of bufif and notif gates. Example 5-3 Gate Instantiations of Bufif Notif Gates Instantiation of bufif gates. bufif1 b1 out in ctrl bufif0 b0 out in ctrl Instantiation of notif gates notif1 n1 out in ctrl notif0 n0 out in ctrl Array of Instances There are many situations when repetitive instances are required. These instances differ from each other only by the index of the vector to which they are connected. To simplify specification of such instances Verilog HDL allows an array of primitive instances to be Example 5-4 shows an example of an array of instances. 1 Refer to the IEEE Standard Verilog Hardware Description Language document for detailed information on the use of an array of instances. Example 5-4 Simple Array of Primitive Instances wire 7 0 OUT IN1 IN2 basic gate instantiations. nand n_gate 7 0 OUT IN1 IN2 This is equivalent to the following 8 instantiations nand n_gate0 OUT 0 IN1 0 IN2 0 nand n_gate1 oUT 1 IN1 1 IN2 1 nand n_gate2 oUT 2 IN1 2 IN2 2 nand n_gate3 oUT 3 IN1 3 IN2 3 nand n_gate4 oUT 4 IN1 4 IN2 4 nand n_gate5 OUT 5 IN1 5 IN2 5 nand n_gate6 OUT 6 IN1 6
