Tuyển tập báo cáo các nghiên cứu khoa học quốc tế ngành hóa học dành cho các bạn yêu hóa học tham khảo đề tài: Research Article SmartCell: An Energy Efﬁcient Coarse-Grained Reconﬁgurable Architecture for Stream-Based Applications | Hindawi Publishing Corporation EURASIP Journal on Embedded Systems Volume 2009 Article ID518659 15 pages doi 2009 518659 Research Article SmartCell An Energy Efficient Coarse-Grained Reconfigurable Architecture for Stream-Based Applications Cao Liang and Xinming Huang Department of Electrical and Computer Engineering Worcester Polytechnic Institute MA 01609 USA Correspondence should be addressed to Xinming Huang xhuang@ Received 2 February 2009 Accepted 15 April 2009 Recommended by Markus Rupp This paper presents SmartCell a novel coarse-grained reconfigurable architecture which tiles a large number of processor elements with reconfigurable interconnection fabrics on a single chip. SmartCell is able to provide high performance and energy efficient processing for stream-based applications. It can be configured to operate in various modes such as SIMD MIMD and systolic array. This paper describes the SmartCell architecture design including processing element reconfigurable interconnection fabrics instruction and control process and configuration scheme. The SmartCell prototype with 64 PEs is implemented using pm CMOS standard cell technology. The core area is about and the power consumption is about MHz. The performance is evaluated through a set of benchmark applications and then compared with FPGA ASIC and two well-known reconfigurable architectures including RaPiD and Montium. The results show that the SmartCell can bridge the performance and flexibility gap between ASIC and FPGA. It is also about 8 and 69 more energy efficient than Montium and RaPiD systems for evaluated benchmarks. Meanwhile SmartCell can achieve 4 and 2 times more throughput gains when comparing with Montium and RaPiD respectively. It is concluded that SmartCell system is a promising reconfigurable and energy efficient architecture for stream processing. Copyright 2009 C. Liang and X. Huang. This is an open access article distributed under the Creative .